Apparatus and method for molding a semiconductor die package with enhanced thermal conductivity

ABSTRACT

A method and apparatus for assembling and packaging semiconductor die assemblies utilizes a coating element such as a wafer backside laminate formed on a backside of a semiconductor die. The coating element may be formed from a somewhat compressible and, optionally, resilient material, which seals against a surface of a mold cavity while the semiconductor die assembly is being encapsulated. In this manner, the coating element prevents encapsulant material from covering at least a portion of the backside of the semiconductor die to prevent encapsulant flashing over the backside and thus improve heat dissipation characteristics of the packaged semiconductor die during operation.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to packaging ofsemiconductor dice and, more specifically, packaging of semiconductordice to provide improved heat dissipation characteristics.

[0003] 2. State of the Art

[0004] During operation, semiconductor devices typically generate largeamounts of heat. The amount of heat that a semiconductor devicegenerates is typically related, if not proportional to, the density offeatures of the semiconductor device. Heat reduces the reliability withwhich semiconductor devices, including processors and memory devices,operate. In addition, the exposure of semiconductor devices to elevatedtemperatures for prolonged periods of time may also decrease the usefullives thereof. Accordingly, the dissipation of heat from semiconductordevices has long been a concern in the semiconductor device industry.

[0005] The reduced power requirements of state-of-the-art semiconductordice have been useful for decreasing the amount of heat generated bysuch semiconductor dice. Nonetheless, as feature densities areever-increasing, the temperatures generated by semiconductor dice witheven reduced power requirements will also continue to increase. Thus,heat dissipation continues to be of concern, even with the low powerrequirements of state-of-the-art semiconductor dice.

[0006] When a semiconductor die is encapsulated, or packaged, the mostdelicate regions thereof, such as the active surface that bearsintegrated circuitry and the bond wires that connect bond pads of thesemiconductor die to corresponding leads of a lead frame or contacts ofa carrier substrate, are covered with a dielectric protective material.In addition, other, more robust surfaces of the semiconductor die, suchas the peripheral edges and backside thereof, are also covered withdielectric protective material. Unfortunately, many of the dielectricprotective materials that are used to encapsulate semiconductor dice arenot good heat conductors. As a result of the manner in which suchdielectric protective materials have been used to coat semiconductordice, a large amount of the heat generated by an encapsulatedsemiconductor die becomes trapped within or around the die.

[0007] Several approaches have been taken to improve the rate at whichheat is transferred and dissipated from packaged semiconductor devices.Conventionally, large surface area structures formed from materials thathave good heat conductivity properties and, thus, which are able to“pull” or transfer heat away from a structure, such as a semiconductordie, contacted thereby have been used to dissipate heat from the packageduring operation of the semiconductor die or dice thereof. These largesurface area structures are generally known in the art as “heat sinks.”Air circulation systems, which often include cooling fans, have alsobeen used, typically in combination with heat sinks or other heatdissipation means. While heat sinks and air circulation systems may beuseful for maintaining conventionally configured semiconductor dice atacceptable operational temperatures in some applications, heat sinks aretypically fairly massive and the size thereof prevents further increasesin the densities at which semiconductor devices are carried upon circuitboards, as is desired to maintain the trend for ever-decreasingelectronic device sizes. In addition, heat sinks may also presentlocational problems between adjacent, superimposed circuit boards andfor space-critical applications such as laptop and notebook computers,cell phones, personal digital assistants and the like.

[0008] As an alternative to the use of space-consuming heat sinks,encapsulation processes have been modified to reduce the amount ofdielectric protective material that covers the surfaces of semiconductordice. Additionally, encapsulation techniques have been developed thatprotect the most delicate portions of a semiconductor die, while leavingother surfaces of the semiconductor die bare, thereby improving heatdissipation therefrom.

[0009] One such technique is described in U.S. Pat. No. 5,604,376 toHamburgen et al. (hereinafter “Hamburgen”), which describes a packagedsemiconductor device in which a backside of a semiconductor die isexposed through an encapsulant to facilitate the dissipation andtransfer of heat from the backside of the semiconductor die. Thepackaged semiconductor device of Hamburgen also includes leads to whichbond pads of the semiconductor die are electrically connected. Theassembly and packaging method described in Hamburgen includestemporarily securing a bare semiconductor die upon a pedestal byapplication of a vacuum through the pedestal to a backside of thesemiconductor die. Leads are then electrically connected tocorresponding bond pads of the semiconductor die by way of conventionalwire bonding processes. Next, the assembly is positioned over a bottomhalf of a mold, with the backside of the semiconductor die resting upona platform. Upon enclosing the semiconductor die and the bond wireswithin a cavity of the mold and as a molding compound is introduced intothe cavity, a negative pressure is applied through an aperture in theplatform to the backside of the semiconductor die, causing the backsideof the semiconductor die to be pulled against the platform andpurportedly preventing the molding compound from flowing onto thebackside of the semiconductor die. This process may be somewhatundesirable for several reasons. For example, as the semiconductor dieand the mold platform therefor are both rigid structures, any deviationsin the planarity or mutual orientation of either the backside of thesemiconductor die or the surface of the platform may permit moldingcompound to flow therebetween. Such planarity deviations, coupled withthe force applied to the semiconductor die to temporarily secure thesame to the mold platform, may also exert potentially damaging stresseson the semiconductor die during the encapsulation process.

[0010] Another example of a packaged semiconductor device that includesa semiconductor die with an exposed backside is described in U.S. Pat.No. 6,348,729 to Li et al. (hereinafter “Li”). The packagedsemiconductor device of Li is formed by attaching an adhesive-coatedtape or film to a surface of a lead frame and securing a semiconductordie to the adhesive-coated tape or film, within a centrally locatedopening of the lead frame. Bond pads of the semiconductor die are thenelectrically connected with corresponding leads of the lead frame byforming or positioning intermediate conductive elements (e.g., bondwires) therebetween. Next, the semiconductor die, intermediateconductive elements, and regions of the leads that are located adjacentto the semiconductor die and above the tape or film are encapsulated.Finally, the tape or film is removed from the packaged semiconductordevice structure (e.g., by peeling). Unfortunately, in addition toexposing the backside of the semiconductor die, surfaces of the leadsare also somewhat undesirably exposed. Exposure of the bottom surfacesof the leads may increase the likelihood of electrical shorting betweenleads as the packaged semiconductor device is positioned upon a carriersubstrate, such as a circuit board. Moreover, upon securing the packagedsemiconductor device of Li to a carrier substrate, the backside of thesemiconductor die thereof will be positioned adjacent or very closely tothe carrier substrate, which may hinder the dissipation of heat from thebackside of the semiconductor die, defeating the intent of exposing thebackside.

[0011] During the preliminary stages of semiconductor device fabricationprocesses, the backsides of silicon wafers and other bulk semiconductorsubstrates are typically adhered to a preformed dielectric protectivefilm, such as a polyimide film. In addition to protecting the backsidesof substrates during fabrication processes and as the substrates arebeing handled and transported from one fabrication process location toanother, these dielectric protective films also retain the positions ofthe various semiconductor devices that have been fabricated on aparticular semiconductor substrate following singulation of thesemiconductor devices, which are, at this point, commonly referred to as“dice,” from one another. The dice may then be tested or otherwiseevaluated, and operable, useful dice picked from the dielectricprotective film for further testing, assembly, or packaging.

[0012] The inventors are not aware of structures that facilitate heatdissipation from a backside of a semiconductor die through a moldedencapsulant while reducing compressional stresses on the semiconductordie during encapsulation thereof and without undesirably increasing thesize of the packaged semiconductor device or causing electricallyconductive structures from being undesirably exposed through theencapsulant.

BRIEF SUMMARY OF THE INVENTION

[0013] The present invention includes methods and apparatus forpackaging semiconductor device assemblies in such a way as to facilitatethe transfer of heat from the backsides of semiconductor dice thereof.

[0014] One aspect of the present invention includes a coating elementfor use on a backside of a semiconductor die. The coating element isconfigured to seal against a surface of a mold cavity during packagingof a semiconductor device assembly of which the semiconductor die is apart to prevent packaging material from covering or “flashing” over thebackside of the semiconductor die. The coating element may also protectthe backside of the semiconductor die during encapsulation of at leastportions of the semiconductor device assembly. Accordingly, the materialof the coating element may be a somewhat compressible or compliant, andresilient, material which is configured to act as a sealant against aninside surface of a mold while packaging the semiconductor deviceassembly. The materials of the coating element may also be compressibleand compliant, but not necessarily resilient so that it remains in asubstantially compressed state after the encapsulation process. Thematerial of the coating element may also be somewhat durable so that thecoating element may protect the die during the assembly andencapsulation processes.

[0015] The backside of a semiconductor die may receive a coating elementprior to severing the semiconductor die from a common substrate uponwhich a plurality of semiconductor dice or other electronic componentshas been fabricated (e.g., at the wafer level), subsequent tosingulating the semiconductor die from a wafer or other commonsubstrate, or following assembly of the semiconductor die with a carriertherefor. The coating element may comprise a preformed, substantiallyplanar element or a quantity of uncured material that will be cured and,optionally, patterned following application thereof to the backside ofthe semiconductor die. The coating element may be applied so as to coversubstantially the entire backside of the semiconductor die or, in avariation, to cover only a portion of the backside of the semiconductordie at or proximate a lateral periphery thereof. In the case of applyingcoating elements onto semiconductor devices that have not yet beensevered or singulated from a common substrate, the coating element maycomprise a single member that substantially covers the backside of thecommon substrate and which is severed as the semiconductor devices thathave been fabricated on the common substrate are singulated from oneanother, or separate coating elements may be formed on or secured to thebacksides of each yet-to-be severed semiconductor device.

[0016] A semiconductor device assembly according to the presentinvention includes one or more semiconductor dice and a carrier. Thecarrier and at least one semiconductor die are oriented in asubstantially parallel manner relative to one another with the backsideof the at least one semiconductor die in the assembly facing outward insuch a way as to contact a surface of a mold cavity during encapsulationof the assembly. The carrier and each semiconductor die assembledtherewith are electrically connected to one another by way ofintermediate conductive elements, such as bond wires, thermocompressionbonded leads, conductive tape-automated bonding (TAB) elements carriedby a dielectric polymeric film, or the like, for electricalinterconnection of the carrier to each semiconductor die thereon.

[0017] In use of a coating element according to the present invention, asemiconductor device assembly including a semiconductor die with acoating element on a backside thereof may be positioned within a cavityof a mold. This may be done by placing a portion of the assembly ineither a first cavity segment of a first mold section or a second cavitysegment of a second mold section. In other words, the semiconductordevice assembly may be positioned with the coating element adjacent amold cavity surface of either mold section. As the first and second moldsections are assembled with one another, the semiconductor deviceassembly is enclosed within the cavity formed by the first and secondcavity segments, with at least a portion of the carrier sitting betweenthe first and second mold sections. With this arrangement, the coatingelement on the backside of a semiconductor die of the assembly may bepositioned and sealed against the inside surface of a cavity half of oneof the mold sections. Molten dielectric encapsulation material may thenbe introduced into the mold under pressure so that particular sensitiveportions of the assembly, such as a lateral periphery and active surfaceof the semiconductor die and the intermediate conductive elementselectrically interconnecting the die to the carrier, are encapsulated.The seal created against the surface of the mold cavity by the coatingelement on the backside of the semiconductor die prevents dielectricencapsulation material from flowing over or flashing onto and, thus,covering a substantial portion of the backside of the semiconductor die.By preventing the dielectric encapsulation material from covering thebackside of the semiconductor die, heat may readily dissipate from thebackside thereof. Further, the coating element provides a compressiblesurface on the backside of the semiconductor die to reduce potentialstresses to the semiconductor die, such as stresses applied to thesemiconductor die from the mold wall abutting the backside, during theencapsulation process.

[0018] The inside surface or wall of a portion of a mold cavity segmentmay include a surface finish of enhanced smoothness relative to thefinish of the remainder of the mold cavity surfaces. Such a finish maybe effected by grinding, lapping or polishing and be at least sized,shaped and positioned on a portion of the inside surface of the moldcavity segment to correspond with the dimensions of the backside of thesemiconductor die. During encapsulation of the assembly, the enhancedsmoothness surface finish provides a surface that readily creates a sealwith the coating element on the backside of the semiconductor die sothat the encapsulation material cannot extrude between the backside ofthe die and the inside surface to form flash on the backside during theencapsulation of portions of the assembly.

[0019] Following encapsulation, the packaged semiconductor deviceassembly may be mounted to higher-level packaging such as a circuitboard for use in an electronic system, such as a computer system. In theelectronic system, the circuit board electrically communicates with aprocessor, which electrically communicates with one or more inputdevices and output devices of the electronic system.

[0020] Other features and advantages of the present invention willbecome apparent to those of skill in the art through a consideration ofthe ensuing description, the accompanying drawings and the appendedclaims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0021] While the specification concludes with claims particularlypointing out and distinctly claiming that which is regarded as thepresent invention, the advantages of this invention may be ascertainedfrom the following description of the invention when read in conjunctionwith the accompanying drawings, wherein:

[0022]FIG. 1 illustrates a simplified side view of a wafer having acoating element disposed thereon, according to the present invention;

[0023]FIG. 2 illustrates a simplified bottom view of a board-on-chipsemiconductor assembly, depicting the coating element disposed oversubstantially an entire back surface of the semiconductor die, accordingto a first embodiment of the present invention;

[0024]FIG. 2(a) illustrates a simplified bottom view of a board-on-chipsemiconductor assembly, depicting the coating element disposed proximatea periphery of the back surface of the semiconductor die, according to avariation of the first embodiment of the present invention;

[0025]FIG. 3 illustrates a simplified cross-sectional side view takenalong line 3-3 in FIG. 2, depicting the board-on-chip semiconductorassembly with bond wires extending between the semiconductor die and thecarrier substrate, according to the first embodiment of the presentinvention;

[0026]FIG. 3(a) illustrates a simplified cross-sectional side view takenalong line 3 a-3 a in FIG. 2(a), depicting the board-on-chipsemiconductor assembly with the coating element disposed proximate theperiphery of the back surface of the semiconductor die, according to avariation of the first embodiment of the present invention;

[0027]FIG. 4 illustrates a simplified cross-sectional side view of theboard-on-chip semiconductor assembly in a mold, depicting a surface ofthe mold abutting a surface of the coating element, according to thefirst embodiment of the present invention;

[0028]FIG. 4(a) illustrates a simplified partial cross-sectional view ofthe mold in an unengaged position with the coating element on thesemiconductor die, according to the present invention;

[0029]FIG. 4(b) illustrates a simplified partial cross-sectional view ofthe mold in an engaged position with the coating element on thesemiconductor die, according to the present invention;

[0030]FIG. 5 illustrates a simplified view of the inside surface of themold, depicting a matte finish and a finely ground finish on the insidesurface, according to the present invention;

[0031]FIG. 6 illustrates a simplified cross-sectional view of aboard-on-chip wire bonded semiconductor package, depicting the coatingelement exposed through the encapsulation material, according to a firstembodiment of the present invention;

[0032]FIG. 7 illustrates a simplified cross-sectional view of aboard-on-chip flip-chip semiconductor package, depicting the coatingelement exposed through the encapsulation material, according to asecond embodiment of the present invention;

[0033]FIG. 8 illustrates a simplified cross-sectional view of alead-on-chip semiconductor package, depicting the coating elementexposed through the encapsulation material, according to a thirdembodiment of the present invention; and

[0034]FIG. 9 illustrates a simplified block diagram of the semiconductorassembly of the present invention integrated in an electronic system.

DETAILED DESCRIPTION OF THE INVENTION

[0035] Embodiments of the present invention will be hereinafterdescribed with reference to the accompanying drawings. It would beunderstood that these illustrations are not to be taken as actual viewsof any specific apparatus or method of the present invention, but aremerely exemplary, idealized representations employed to more clearly andfully depict the present invention than might otherwise be possible.Additionally, elements and features common between the drawing figuresretain the same or similar reference numerals.

[0036]FIG. 1 illustrates a side view of a wafer 100. Wafer 100 includesmultiple semiconductor dice 110 in a physically interconnected array ofcolumns and rows (not shown), each semiconductor die 110 distinguishedfrom others on wafer 100 by broken lines 118, along which thesemiconductor dice are separated or singulated, as by sawing orscribing. Wafer 100, and each of the multiple semiconductor dice 110thereof, includes an active surface 112 and a backside 114. The wafer100 is formed from a semiconducting material and is preferably formedfrom silicon, but may be formed from gallium arsenide, indium phosphideor any other known semiconducting material, the electrical conductivityand resistivity of which lie between those of a conductor and aninsulator. Other bulk substrates, including partial wafers, as well assilicon-on-insulator (SOI) substrates (e.g., silicon-on-glass (SOG),silicon-on-ceramic (SOC), silicon-on-sapphire (SOS), etc.) are alsowithin the scope of the present invention and included within themeaning of the term “wafer.”

[0037] According to the present invention, wafer 100 may receive acoating element 150 formed on the backside 114 thereof. Coating element150 is configured to be compressible or compliant so as to act as asealant, which will be further described herein. Coating element 150 maybe a coating element applied to the semiconductor dice 110 to reducestresses thereto and/or prevent chipping of the backside 114 thereofduring procedures of testing, general handling, singulation andencapsulation procedures. Coating element 150 may be configured toreadily conduct and dissipate heat, wherein coating element 150 providesa surface that easily allows heat to dissipate from the semiconductordice 110. The coating element 150 may have a coefficient of thermalexpansion (CTE) similar to that of the adjacent semiconductor orinsulator (in the case of nonwafer bulk substrates) material.

[0038] Coating element 150 may be applied to the backside 114 of each ofthe semiconductor dice 110 by flowing a polyimide material thereon(e.g., by known spin-on, screen printing, spray-on, or spreadingprocesses). Such a technique may be especially desirable to employ atthe wafer scale. If required, filler material, such as polysilicon, maybe added to the polyimide material to adjust the coefficient of thermalexpansion to substantially match the coefficient of thermal expansion ofthe backside 114 of the semiconductor die 110. A photosensitive materialsuch as is employed for etch masking may also be applied, exposed, anddeveloped and undesired portions of the coating element 150 removed fromthe backsides 114 of semiconductor dice 110, individually but preferablyat the wafer scale. In the alternative, the coating element 150 may bealready prepared as a preformed polyimide sheet or film, wherein thepolyimide sheet or film may be adhesively attached to the backside 114of the semiconductor die 110 using, for example, a pressure-sensitiveadhesive. Such a structure may be termed a “wafer backside laminate.” Asa further variation, a resin may be applied to a sheet, tape or film toform a composite coating element providing sufficient adherency to thewafer 100 or a semiconductor die 110 along with sufficient resiliencyand compressibility. The resin may provide adhesion for the sheet, tapeor film to the backsides 114 of semiconductor dice 110.

[0039] In whatever form, coating element 150 may be of sufficientthickness such that, in combination with a selected compressibility, itaccommodates when compressed at least an average bondline deviation (thedeviation between the semiconductor die surface and carrier substrate,such as an interposer, surface during die mount) of between about 20 and30 μm to prevent flash over the backside 114 during encapsulation. Thus,for example and without limitation, an initial, resiliently compressiblecoating element thickness of between about 50 and 100 μm may be used toallow for and accommodate bondline deviation while still minimizing theheight of the finished package and any thermal barrier to heat transferfrom the backside 114 of semiconductor die 110.

[0040] The wafer 100 may be singulated along broken lines 118 to providemultiple semiconductor dice 110. The coating element 150 may be disposedon the backside 114 of each of the semiconductor dice 110 prior to, orsubsequent to, singulation thereof from the wafer 100. In either case,each of the individual semiconductor dice 110 receives the coatingelement 150 prior to a die attach process wherein a semiconductor die110 is secured to a carrier substrate such as an interposer or leadframe.

[0041]FIG. 2 illustrates a bottom view of a board-on-chip (BOC) assemblysubsequent to the die attach process. The singulated semiconductor die110 having the coating element 150 formed on a backside 114 thereof maybe attached to a carrier substrate 120. Specifically, as shown, thesemiconductor die 110 is attached with its active surface toward thecarrier substrate 120 so that the coating element 150 is facing outward.

[0042]FIG. 3 is a cross-sectional view taken along line-3-3 in FIG. 2,illustrating the carrier substrate 120 and semiconductor die 110 and theinterconnections therebetween. The carrier substrate 110 includes afirst surface 122 and a second surface 124 with an opening 126 that maybe centrally located in the carrier substrate 120 and extends betweenthe first surface 122 and the second surface 124 on the carriersubstrate 120. Carrier substrate 120 may be any suitable carrier-typesubstrate known in the art, such as an interposer or printed circuitboard. Carrier substrate 120 may also be made of any type of substratematerial known in the art, such as bismaleimide triazine (BT) resin,ceramics, flexible polyimides, FR-4 or FR-5 materials, glass,insulator-coated silicon, or the like.

[0043] The semiconductor die 110 includes an active surface 112 and abackside 114 with bond pads 116 formed on the active surface 112thereof. The bond pads 116 may be centrally located and exposed on theactive surface 112 of the semiconductor die 110 and interconnected withintegrated circuitry (not shown) on the active surface 112 of thesemiconductor die 110. With this arrangement, the carrier substrate 120may be secured to a peripheral region of the active surface 112 of thesemiconductor die 110 so that the bond pads 116 may be exposed throughthe opening 126 of the carrier substrate 120. The semiconductor die 110may be attached to the carrier substrate 120 with one or more adhesiveelements 130. The adhesive element 130 may be any known adhesivestructure, such as an adhesive decal, adhesive-coated tape, a liquid orgel adhesive material, or the like. Bond wires 132 or other intermediateconductive elements (e.g., conductive tape-automated bonding (TAB)conductive elements carried upon a dielectric polymer film,thermocompression-bonded leads, etc.) may then be formed or extendedbetween the bond pads 116 on the active surface 112 of the semiconductordie 110 and their corresponding conductive pads 128 on the secondsurface 124 of the carrier substrate 120, with bond wires 132 or otherintermediate conductive elements extending through the opening 126.

[0044] As illustrated in FIGS. 2 and 3, the coating element 150 maysubstantially cover the entire backside 114 of the semiconductor die 110and face outward from the assembled semiconductor die 110 and carriersubstrate 120.

[0045]FIG. 2(a) illustrates a variation of the coating element 150. Inthis variation, coating element 150′ is disposed on the backside 114 andforms a frame proximate only a periphery 115 of the semiconductor die110. This variation provides that a central portion of the backside 114of the semiconductor die 110 is left without the coating element 150′.In this alternative, it is contemplated that the coating element 150′may be applied to the backside 114 utilizing a masking and patterningtype process, as is well known in the art, using a positive or negativephotoresist. Coating element 150′ may also be applied by use of astencil, as is also known. The coating element 150′ may be applied tothe backside 114 at a wafer level or to each semiconductor die 110 on anindividual basis.

[0046] Illustrated in FIG. 3(a) is a cross-sectional bottom view takenalong line 3 a-3 a in FIG. 2(a), depicting the carrier substrate 120 andsemiconductor die 110 with the coating element 150′ on the backside 114of the semiconductor die 110 according to a variation of the firstembodiment. In particular, the coating element 150′ is provided on thebackside 114 proximate periphery 115 of the semiconductor die 110 sothat a central portion of the backside 114 is left without the coatingelement 150′.

[0047] Turning to FIG. 4, the board-on-chip assembly is positioned in amold 140 preparatory to encapsulating the assembly in a transfer moldingprocess. The term “transfer molding” is descriptive of an example ofthis process, as a filled polymer thermoplastic molding compound, in aliquid or molten state, is transferred under pressure to a plurality ofremotely located mold cavities containing semiconductor deviceassemblies to be encapsulated. However, for purposes of simplicity, onlyone mold cavity 146 associated with the mold 140 is depicted in drawingFIG. 4. Pot molding processes, injection molding processes and otherencapsulation techniques may also be used with, and benefit from, thepresent invention.

[0048] The mold 140 includes a first mold section 142 and a second moldsection 144, each of which includes recesses that together form multiplemold cavities, such as the depicted mold cavity 146. The mold cavity 146is sized and configured to contain the semiconductor die 110 in theassembly and, specifically, an inside surface 148 of the mold 140 isconfigured with at least a portion located and oriented to abut with thecoating element 150 on the backside 114 of the semiconductor die 110.The mold cavity 146 is also sized and configured to contain, withoutcontacting, the bond wires 132 or other intermediate conductive elementsthat electrically interconnect the semiconductor die 110 to the carriersubstrate 120. In this manner, the mold cavity 146 is filled with adielectric encapsulation material 134 (FIG. 6), such as a moldingcompound introduced by transfer or injection molding, to coat, cover andprotect at least a periphery of the semiconductor die 110, the bondwires 132, bond pads 116 and conductive pads 128.

[0049] Each mold cavity 146 in a transfer mold includes a gate and vent(not shown), as known in the art. The gate is used as an inlet for athermoplastic dielectric encapsulation material 134 to flow into themold cavity 146. The vent, typically located at an opposite end of themold cavity 146 from the gate, permits air or other gases in the moldcavity 146 to be displaced by the wave front of the dielectricencapsulation material and escape from the mold cavity 146 uponintroduction of the dielectric encapsulation material 134 thereinto.After entry into the mold cavity 146, the dielectric encapsulationmaterial 134 solidifies and forms a part of the semiconductor deviceassembly.

[0050] FIGS. 4(a) and 4(b) illustrate the semiconductor die 110 and aninside surface 148 of the mold 140 in an unengaged position and a fullyengaged position, respectively. According to the present invention, theinside surface 148 of the mold 140 may include some regions with arelatively smoother, ground, lapped or polished finish 154 and otherregions with a rougher, matte finish 156. The area of the enhancedsmoothness finish 154 is substantially sized and shaped to correspondwith the backside 114 of the semiconductor die 110 and may be squareshaped and centrally located within the matte finish 156 area, asdepicted in FIG. 5, illustrating a top inside view of the central,bottom portion B and side portions S of the mold cavity segment of thefirst mold section 142. The matte finish 156 area may comprise the raw,as cast or machined, inside surface 148 of the mold 140 without furthergrinding or polishing thereof. With respect to the enhanced smoothnessfinish 154 area, it exhibits a fine finish, such as a ground, lapped orpolished finish, having a surface topography configured to facilitate aseal 158 between the coating element 150 and the inside surface 148 ofthe mold 140. The seal 158 is provided by coating element 150 when thesemiconductor die 110 is in the fully engaged position with the firstmold section 142, such as when the first and second mold sections 142and 144 are assembled with one another. In this manner, seal 158provided by the coating element 150 resiliently compressed between thesemiconductor die 110 and the first mold section 142 in the fullyengaged position is configured to prevent the encapsulation material 134from flowing over, and flashing onto, the backside 114 of thesemiconductor die 110.

[0051] It will be appreciated that, once the semiconductor die 110 hasbeen removed from the mold cavity 146, coating element 150 may remain ina substantially compressed state and thus have an outer surfacesubstantially coplanar with that of the hardened dielectricencapsulation material 134 surrounding the coating element 150.Alternatively, the coating element 150 may have sufficient resiliency soas to spring back to an uncompressed thickness or to regain at least aportion thereof, in which instance the outer surface of the coatingelement 150 may project slightly above the outer surface of thesurrounding, hardened dielectric encapsulation material 134.

[0052] Turning to FIG. 6, a board-on-chip semiconductor package 160having portions of the semiconductor die 110 and carrier substrate 120and the electrical interconnections therebetween encapsulated bydielectric encapsulation material 134 is illustrated. A significantaspect of the present invention is exposure in the finishedsemiconductor device package of the relatively thin coating element 150through the encapsulation material 134 on the backside 114 of thesemiconductor die 110. With this arrangement, heat may readily transferthrough the substrate of semiconductor die 110 from the active surface112 and dissipate from the backside 114 of the semiconductor die 110. Itis notable that coating element 150, due to its relative thinness, isnot a significant impediment to heat transfer from the semiconductor die110 and thus need not be removed from backside 114 and remains as partof semiconductor package 160. If desired, coating element 150 may becolored and may include graphics thereon to identify the manufacturer,part number, etc. Alternatively, coating element 150 may be formulatedto be sensitive to heat or to specific wavelengths of electromagneticradiation to facilitate marking, as by a laser, of the semiconductorpackage after fabrication as well as after various stages of testing. Asshown at 170, a plurality of discrete conductive elements in the form ofsolder bumps, conductive or conductor-filled epoxy pillars or columns orother suitable structures may be applied to or formed on carriersubstrate 120 in communication with conductive traces (not shown) ofcarrier substrate 120 extending to conductive pads 128 to provideexternal electrical connections from semiconductor die 110 tohigher-level packaging.

[0053]FIG. 7 illustrates a second embodiment of a semiconductor package260. The semiconductor package 260 includes a flip-chip type assembly,wherein a semiconductor die 210 is attached facedown to a carriersubstrate 220 with discrete conductive elements such as conductive bumps232 therebetween. The semiconductor die 210 includes an active surface212 and a backside 214, wherein the backside 214 includes coatingelement 250 disposed thereon. The carrier substrate 220 includes a firstsurface 222 and a second surface 224. The conductive bumps 232electrically and mechanically interconnect the semiconductor die 210 tothe carrier substrate 220 by being disposed between and bonded to bondpads 216 on the active surface 212 of the semiconductor die 210 andconductive pads 226 on the first surface 222 of the carrier substrate220. A dielectric encapsulation material 234 is introduced in a gapbetween the semiconductor die 210 and carrier substrate 220, as well asaround a periphery 211 of the semiconductor die 210. Similar in fashionto the first embodiment, the backside 214 of the semiconductor die 210having coating element 250 thereon is exposed through the encapsulationmaterial 234, thereby providing an outlet for heat to dissipate from thesemiconductor die 210. Further, the exposed coating element 250 seals toan inside surface of a mold (not shown) during the encapsulationprocess, in a manner similar to that described in the first embodiment.

[0054] With respect to FIG. 8, a third embodiment of a semiconductorpackage 360 is illustrated. Semiconductor package 360 includes aleads-over-chip (LOC) type assembly, wherein there is a carrier 320, orleads, attached to an active surface 312 of a semiconductor die 310 viaadhesive tape 330 or the like. The carrier 320 includes a first surface322 and a second surface 324 and is electrically interconnected to thesemiconductor die 310 by bond wires 332 or other intermediate conductiveelements extending from bond pads 316 on the active surface 312 of thesemiconductor die 310 to conductive pads 338 on second surface 324 ofthe carrier 320. The backside 314 of the semiconductor die 310 includescoating element 350 disposed thereon. With this arrangement, theleads-over-chip assembly may be encapsulated in a mold (not shown) withencapsulation material 334 to encapsulate portions of the semiconductordie 310, the carrier 320 and the bond wires 332 and interconnectionsthereof. As in the previous embodiments, the coating element 350 isexposed through the encapsulation material 334. Such an exposed coatingelement 350 may provide an outlet for heat to dissipate from thesemiconductor die 310. Other types of lead frame-type assemblies may beutilized in the present invention as long as the coating element 350 onthe backside 314 of the semiconductor die 310 is exposed through theencapsulation material 334 to provide a heat dissipation outlet for thesemiconductor package 360.

[0055] As illustrated in block diagram form in drawing FIG. 9,semiconductor packages 160, 260 and/or 360 may be mounted to a circuitboard 410 in an electronic system 400, such as a computer system. In theelectronic system 400, the circuit board 410 may be connected to aprocessor device 420 which communicates with an input device 430 and anoutput device 440. The input device 430 may comprise a keyboard, mouse,joystick or any other type of electronic input device. The output device440 may comprise a monitor, printer or storage device, such as a diskdrive, or any other type of output device. The processor device 420 maybe, but is not limited to, a microprocessor or a circuit card includinghardware for processing instructions for the electronic system 400.Additional structure for the electronic system 400 is readily apparentto those of ordinary skill in the art.

[0056] While the present invention has been disclosed with reference tocertain illustrated embodiments, those of ordinary skill in the art willrecognize and appreciate that it is not so limited. Rather, additions,deletions and modifications to the illustrated embodiments may be made,and features and elements from one embodiment employed, as appropriate,in another. In addition, the coating element of the present inventionmay be applied between the die and a carrier substrate such as aninterposer to accommodate bondline deviation and provide the necessaryresiliency while leaving the backside of the die bare. Further, thecoating element may be placed on the side of the carrier substrateopposite the semiconductor die for bondline deviation accommodation andto provide compressibility. The present invention and the scope thereofis defined by the following claims and equivalents of the elements,features and acts recited therein.

What is claimed is:
 1. A semiconductor device assembly, comprising: atleast one semiconductor die; a carrier positioned adjacent to an activesurface of the at least one semiconductor die and including at least aportion oriented substantially parallel thereto; at least oneintermediate conductive element electrically connecting at least onebond pad of the at least one semiconductor die and a correspondingcontact of the carrier; an encapsulant covering at least an outerperiphery of the at least one semiconductor die; and a coating elementon at least a portion of a backside of the at least one semiconductordie, at least a substantial portion of the coating element beingexposed.
 2. The semiconductor device assembly of claim 1, wherein thecoating element is sized and shaped in substantial conformance to a sizeand shape of the backside of the at least one semiconductor die.
 3. Thesemiconductor device assembly of claim 1, wherein the coating elementhas an outer surface substantially coplanar with an outer surface ofencapsulant.
 4. The semiconductor device assembly of claim 1, wherein anouter surface of the coating element projects slightly beyond asurrounding outer surface of encapsulant.
 5. The semiconductor deviceassembly of claim 1, wherein the coating element substantially coversthe backside of the at least one semiconductor die.
 6. The semiconductordevice assembly of claim 1, wherein the coating element includes anouter boundary lying substantially along a periphery of the backside ofthe at least one semiconductor die.
 7. The semiconductor device assemblyof claim 6, wherein the coating element is configured as a frame.
 8. Thesemiconductor device assembly of claim 6, wherein the coating element isconfigured so that a nonperipheral portion of the backside of the atleast one semiconductor die is exposed.
 9. The semiconductor deviceassembly of claim 6, wherein the coating element is configured so that acentral portion of the backside is exposed.
 10. The semiconductor deviceassembly of claim 1, wherein the coating element comprises a somewhatcompressible and, optionally, resilient material.
 11. The semiconductordevice assembly of claim 1, wherein the coating element comprises apreformed film.
 12. The semiconductor device assembly of claim 11,wherein the preformed film is adhered to the at least a portion of thebackside with an adhesive.
 13. The semiconductor device assembly ofclaim 1, wherein the coating element is formed on the at least a portionof the backside in a nonsolid state and subsequently at leastsubstantially solidified.
 14. The semiconductor device assembly of claim1, wherein the coating element is formulated to exhibit a coefficient ofthermal expansion similar to a coefficient of thermal expansion of theat least one semiconductor die.
 15. The semiconductor device assembly ofclaim 14, wherein the coating element comprises a preformed film filledwith silicon particles.
 16. The semiconductor device assembly of claim14, wherein the coating element is formed on the at least a portion ofthe backside in a nonsolid mass filled with silicon particles andsubsequently at least substantially solidified.
 17. The semiconductordevice assembly of claim 1, wherein the encapsulant substantiallyencapsulates the at least one intermediate conductive element.
 18. Thesemiconductor device assembly of claim 1, wherein the encapsulant coversat least a portion of the carrier.
 19. The semiconductor device assemblyof claim 1, wherein the carrier includes at least one aperture throughwhich the at least one bond pad of the at least one semiconductor die isexposed and the at least one intermediate conductive element extendsthrough the at least one aperture between the at least one bond bad andthe corresponding contact of the carrier.
 20. The semiconductor deviceassembly of claim 1, wherein the corresponding contact is on a surfaceof the carrier facing the active surface of the at least onesemiconductor die and in alignment therewith and the carrier is spacedfrom the at least one semiconductor die by the at least one intermediateconductive element.
 21. The semiconductor device assembly of claim 20,wherein the at least one bond pad comprises an array of bond pads. 22.The semiconductor device assembly of claim 21, wherein the at least oneintermediate conductive element comprises a conductive bump, aconductive pillar, or a conductive pin.
 23. The semiconductor deviceassembly of claim 20, wherein the encapsulant extends between thecarrier and the at least one semiconductor die and encapsulates the atleast one intermediate conductive element therebetween.
 24. Thesemiconductor device assembly of claim 1, wherein the carrier comprisesa lead frame and the corresponding contact comprises a lead finger. 25.A mold assembly configured for use in packaging a semiconductor die on acarrier, the mold assembly comprising: at least first and second moldsections to be assembled with one another; at least one cavity segmentformed in each of the first and second mold sections, the at least onecavity segment in each of the first and second mold sections being sizedand configured, when in alignment, to define at least one cavityconfigured to receive a semiconductor die on a carrier; a portion of aninner surface of the at least one cavity segment of at least one of thefirst and second mold sections comprising a surface finish of enhancedsmoothness relative to at least one other portion of the inner surface.26. The mold assembly of claim 25, wherein the portion of the innersurface is substantially centrally located in the at least one cavitysegment.
 27. The mold assembly of claim 25, wherein the portion of theinner surface is positioned on the inner surface to correspond with alocation of a backside of the semiconductor die on the carrier whenreceived in the at least one cavity.
 28. The mold assembly of claim 27,wherein the portion of the inner surface has an outer peripherysubstantially coincident with the backside of the semiconductor die. 29.The mold assembly of claim 25, wherein the surface finish of the portionof the inner surface comprises a ground finish, a lapped finish or apolished finish.
 30. The mold assembly of claim 25, wherein the portionof the inner surface is shaped as a frame.
 31. A method for packaging asemiconductor device assembly, comprising: providing a semiconductordevice assembly including at least one semiconductor die and a carriertherefor positioned adjacent to an active surface thereof; applying acoating element defining an outer periphery to a backside of the atleast one semiconductor die; positioning the semiconductor deviceassembly within a cavity of a mold, with the coating element between thebackside of the at least one semiconductor die and an inner surface ofthe cavity; and introducing an encapsulant into the cavity toencapsulate at least a periphery of the at least one semiconductor diewhile preventing encapsulant flash over a portion of the backside of theat least one semiconductor die within the outer periphery of the coatingelement.
 32. The method of claim 31, wherein applying the coatingelement comprises applying a somewhat compressible and, optionally,resilient material to the backside of the at least one semiconductordie.
 33. The method of claim 32, further comprising, following thepositioning and responsive to enclosing the semiconductor deviceassembly within the cavity, compressing the material between thebackside and the inner surface of the cavity.
 34. The method of claim33, wherein compressing comprises forming a seal to prevent theencapsulant from flashing over the backside of the at least onesemiconductor die.
 35. The method of claim 31, wherein positioningcomprises forming a seal between the backside of the at least onesemiconductor die and the inner surface of the cavity.
 36. The method ofclaim 35, wherein forming a seal comprises accommodating for anybond-line deviation.
 37. The method of claim 31, wherein applyingcomprises applying the coating element to the backside to extendproximate a periphery of the backside of the at least one semiconductordie.
 38. The method of claim 31, wherein applying comprises applying thecoating element to the backside of the at least one semiconductor die sothat a central portion of the backside is exposed.
 39. The method ofclaim 31, further comprising providing a surface finish of enhancedsmoothness relative to at least one other portion of the inner surfaceon a portion of the inner surface of the cavity within a location of theouter periphery of the coating element when the semiconductor deviceassembly is received within the cavity.
 40. The method of claim 39,wherein providing a surface finish of enhanced smoothness on the portionof the inner surface of the cavity within a location of the outerperiphery of the coating element comprises providing the surface finishwithin an entirety of the outer periphery.
 41. A method for enhancingthermal dissipation characteristics of a packaged semiconductor device,comprising: providing an assembly including at least one semiconductordie and a carrier therefor positioned adjacent to an active surfacethereof, the assembly including at least one intermediate conductiveelement electrically connecting a bond pad of the at least onesemiconductor die and a corresponding contact of the carrier; applying acoating element to at least a portion of the backside of the at leastone semiconductor die; encapsulating at least a portion of the assemblywith an encapsulant material; and leaving the coating element exposed.42. The method of claim 41, wherein applying the coating elementcomprises applying a somewhat compressible and, optionally, resilientmaterial to the backside of the at least one semiconductor die.
 43. Themethod of claim 41, wherein applying the coating element comprisesapplying the coating element to the backside at least proximate aperiphery of the at least one semiconductor die.
 44. The method of claim41, wherein applying the coating element comprises applying the coatingelement to the backside so that a central portion of the backside isexposed.
 45. The method of claim 41, wherein leaving the coating elementexposed includes leaving an outer surface thereof exposed andsubstantially coplanar with an outer surface of encapsulant material.46. The method of claim 41, wherein leaving the coating element exposedincludes permitting an outer surface of the coating element to projectslightly beyond a surrounding outer surface of encapsulant.
 47. Themethod of claim 41, further including applying the coating element tosubstantially cover the backside of the at least one semiconductor die.48. The method of claim 41, further including applying the coatingelement so that an outer boundary thereof lies substantially along aperiphery of the backside of the at least one semiconductor die.
 49. Themethod of claim 48, further including configuring the coating element asa frame.
 50. The method of claim 48, further including configuring thecoating element so that a nonperipheral portion of the backside of theat least one semiconductor die is exposed.
 51. The method of claim 48,further including configuring the coating element so that a centralportion of the backside is exposed.
 52. The method of claim 41, furtherincluding forming the coating element of a somewhat compressible and,optionally, resilient material.
 53. The method of claim 41, furtherincluding applying the coating element as a preformed film.
 54. Themethod of claim 53, further including adhering the preformed film to thebackside of the at least one semiconductor die with an adhesive.
 55. Themethod of claim 41, wherein applying comprises applying the coatingelement to the backside in a nonsolid state and subsequently at leastsubstantially solidifying the coating element.
 56. The method of claim41, further including formulating the coating element to exhibit acoefficient of thermal expansion similar to a coefficient of thermalexpansion of the at least one semiconductor die.
 57. The method of claim56, further including fabricating the coating element as a preformedfilm filled with silicon particles.
 58. The method of claim 56, furtherincluding applying the coating element to the backside of the at leastone semiconductor die as a nonsolid mass filled with silicon particlesand subsequently at least substantially solidifying the mass.
 59. Themethod of claim 41, further including substantially encapsulating the atleast one intermediate conductive element with encapsulant material. 60.The method of claim 41, further including covering at least a portion ofthe carrier with encapsulant material.
 61. An intermediate structure fora semiconductor device assembly, comprising: a semiconductor die securedto a carrier and operably coupled thereto for external electricalcommunication therethrough; and a coating element positioned on abackside of the semiconductor die adjacent to at least a peripheral edgeof the backside, the coating element comprising a material for sealingbetween the backside of the semiconductor die and an inner surface of amold cavity to prevent an encapsulant material introduced into the moldcavity from covering the backside of the semiconductor die duringencapsulation of the intermediate structure in the mold cavity.
 62. Theintermediate structure of claim 61, wherein the coating element is sizedand configured to substantially cover the backside of the semiconductordie.
 63. The intermediate structure of claim 61, wherein the coatingelement is sized and configured to substantially overlie the backside ofthe semiconductor die proximate a peripheral edge thereof.
 64. Theintermediate structure of claim 63, wherein the coating element is sizedand configured so that a portion of the backside of the semiconductordie is exposed.
 65. The intermediate structure of claim 61, wherein thecoating element comprises a somewhat compressible and, optionally,resilient material.
 66. The intermediate structure of claim 61, whereinthe coating element exhibits a coefficient of thermal expansion similarto a coefficient of thermal expansion of the semiconductor die.
 67. Anelectronic system comprising: a processor in communication with at leastone input device and at least one output device; and a semiconductorassembly, comprising: at least one semiconductor die; a carrierpositioned adjacent to an active surface of the at least onesemiconductor die and oriented substantially parallel thereto, thecarrier being in communication with at least one of the processor, theat least one input element, and the at least one output element; atleast one intermediate conductive element electrically connecting a bondpad of the at least one semiconductor die and a corresponding contact ofthe carrier; an encapsulant covering at least an outer periphery of theat least one semiconductor die; and a coating element on a backside ofthe at least one semiconductor die, at least a substantial portion ofthe coating element being exposed
 68. The electronic system of claim 67,wherein the coating element comprises a layer that substantially coversthe backside of the at least one semiconductor die.
 69. The electronicsystem of claim 67, wherein the coating element comprises a layer thatoverlies the backside at least proximate an outer periphery of thebackside of the at least one semiconductor die.
 70. The electronicsystem of claim 69, wherein the layer is configured so that a portion ofthe backside of the at least one semiconductor die is exposed.
 71. Theelectronic system of claim 67, wherein the coating element is positionedon the backside of the at least one semiconductor die adjacent to anouter periphery thereof, a central portion of the backside remainingexposed.
 72. The electronic system of claim 67, wherein the coatingelement comprises a somewhat compressible and, optionally, resilientmaterial.
 73. The electronic system of claim 67, wherein the coatingelement exhibits a coefficient of thermal expansion similar to acoefficient of thermal expansion of the at least one semiconductor die.74. The electronic system of claim 67, wherein the encapsulantsubstantially encapsulates the at least one intermediate conductiveelement.